MITS has secured NIRF India Ranking 2024 in the band 201 to 300.
Dr. Vivek Jain

Qualification : Ph.D. (Devi Ahilya Vishwavidyalay, Govt. University)

Designation : Asst. Professor

Details of Educational Qualification:

Course Specialization Group College Name/University Year of Passing
Ph.D Electronics and Communication Electronics and Communication Devi Ahilya Vishwavidyalaya (DAVV, Indore), Govt. University 2021
M.Tech. Microelectronics & VLSI Design Microelectronics & VLSI Design S.G.S.I.T.S., Indore 2010
B.E. Electronics & Communication Electronics & Communication HCET, Jabalpur, RGPV Bhopal 2002

 

My Publications

S.No Title of the Paper Full Details of Journal Name / Conference Name, Volume number, page number, Date
1 “Machine Learning Approach for Image based Plant Leaf Disease Identification with Performance Improvement” Journal of Information and Computational Science (JOICS), ISSN: 1548-7741, vol. 12, issue 06, pp. 19-23, Jun 2022. https://drive.google.com/file/d/1Bq1XWrnGqth8ycJ-MWlEx-I-ZGyYro1C/view
2 “Plant Leaf Disease Identification using Machine Learning Techniques: A Review” International Journal of Innovative Research in Computer and Communication Engineering (IJIRCCE),ISSN: 2320-9801, vol. 10, issue 03, pp. 1609- 1613, Mar 2022. http://ijircce.com/admin/main/storage/app/pdf/tLySqYygOvMaPLPHzOkBNf5iImxctz5bMvQNu Wzo.pdf
3 “Implementation of Self Cascode based Efficient Charge Recovery Logic for Ultra Low Power Applications” International Conference on Computing, Communication and Control (ICCCC-2020) ISBN: 978-93-89107-79-1, Feb 2020.
4 “Implementation of Self Cascode based Efficient Charge Recovery Logic for Ultra Low Power Applications” International Conference on Computing, Communication and Control (ICCCC-2020) ISBN: 978-93-89107-79-1, Feb 2020.
5 “Energy efficient digital circuit based on self cascoding positive feedback adiabatic logic for low power VLSI design” International Journal of Recent Technology and Engg.(IJRTE), ISSN: 2277-3878, vol. 08, pp. 950-954, Sep, 2019. https://www.ijrte.org/wp-content/uploads/papers/v8i2S11/B11570982S1119.pdf
6 “A self cascode based subthreshold positive feedback adiabatic logic for ultra low power applications” International Journal of Innovative Technology and Creative Engineering (IJITCE), ISSN: 2045-8711, vol. 08, no.10, pp. 543- 549, Oct, 2018. https://ia803100.us.archive.org/23/items/vol8no1002/vol8no1002.pdf
7 “Design and analysis of energy efficient MOS digital library cell based on charge recovery logic” International Journal of Computational Engg. and Research (IJCER), ISSN: 2250-3005, vol. 08, issue 09, pp. 42-47, Sep 2018. http://www.ijceronline.com/papers/Vol8_issue9/Version-2/G0809024247.pdf
8 “Design of energy efficient MOS digital circuit for low power VLSI design” International Journal of VLSI and Embedded System-IJVES, ISSN: 2249-6556, vol. 07, pp. 1660-1664, May 2016.
9 “Study and Analysis of Single Port Smart Antenna Systems in wireless communication application” Paper Id EC/O/03”, National Conference AECE-2013” SVIT, Indore.
10 “Studies and Analysis of Single Port Smart Antenna in wireless communication system and its applications” National Conference, AEEE-2013 at S.V.C.E. Indore,M.P.
11 “Cryptography using MATLAB” Proc. of National Conference TRIEECON, SAIT, Indore, 2012.
12 “Study and Analysis of a Smart antenna in wireless LAN communication system” International Conference on Computers and Communication (ICCC-2012),SIRT, Bhopal.
13 “An Efficient Design of High Speed, Low Power Comparator using 180 nm CMOS Technology” Proc. of National Conference TRIEECON 2012, SAIT, Indore, India.
14 “CMOS based Wide Band Current Conveyor” National Conference ATHENA, SIRT, Bhopal, M.P., 2009.