Dr. Grande Naga Jyothi
Qualification : Ph.D. (VIT University)
Designation : Asst. Professor
Details of Educational Qualification:
| Course | Specialization | Group | College Name/University | Year of Passing |
|---|---|---|---|---|
| Ph.D. | Digital FIR filter architecture in VLSI | Electronics and Communication Engineering | VIT University | 2020 |
| M.Tech. | VLSI Design | Electronics and Communication Engineering | VIT University | 2008 |
| B.Tech. | Electrical & Electronics Engineering | Electrical & Electronics Engineering | JNTU University, Anantapur | 2006 |
List of Publications
| S.No | Title of the Paper | Full Details of Journal Name / Conference Name, Volume number, page number, Date |
|---|---|---|
| 1 | ”Enhancing Network forensic and deep learning mechanism for Internet of Things networks” | Journal of scientific and industrial research (JSIR) 2022-SCI-accepted |
| 2 | ”Multiple Degradation Skilled Network for Infrared and Visible Image Fusion Based on Multi-Resolution SVD Updation.” | Mathematics 10.18 (2022): 3389. |
| 3 | ”Designing a fuzzy Q-learning Power Energy system using reinforcement learning”.International journal of fuzzy system Application”. | IGI global Free scopus 2022.Free Scopus |
| 4 | ”Utilization of IoT-assisted computational strategies in wireless sensor networks for smart infrastructure management”. | International Journal of System Assurance Engineering and Management-Springer free ESCI.2022. |
| 5 | ”High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter.” | Multimedia Tools and Applications-Springer Free Scopus Impact Factor journal-2.1(2019): 1-15. |
| 6 | ”ASIC Implementation of Linear equalizer using FIR Filters” | IGI publishers; International Journal of e-Collabration; (2020) Free Scopus Impact factor Journal-0.12 . |
| 7 | ”Low Power, Low Area Adaptive FIR Filter Based on Memory Less Distributed Arithmetic.” | J. Comput. Theor. Nanosci 15 (2018): 1-6. |
| 8 | ”Low Power Design of 2–4 and 4–16 Line Decoders,” | International Journal of Innovative Technology and Exploring Engineering (IJTEE) (2019). |
| 9 | ”High speed low area OBC DA based decimation filter for hearing aids application.” | International Journal of Speech Technology (2019): 1-11.-Springer; Free Scopus. |
| 10 | ”ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems.” | International Journal of Speech Technology: 1-6.(2020)-Springer; Free Scopus. |
| 11 | ”Distributed arithmetic architectures for FIR filters-A comparative review.” | Wireless Communications, Signal Processing and Networking (WiSPNET), 2017 International Conference on. IEEE, 2017. |
| 12 | ”ASIC implementation of shared LUT based distributed arithmetic in FIR Filter.” | Microelectronic Devices, Circuits and Systems (ICMDCS), 2017 International conference on. IEEE, 2017. |
| 13 | ”A Low Power 10 bit 50-MS/s Sample and Hold OTA Amplifier.” | Proceedings of the 2018 International Conference on Communication Engineering and Technology. ACM-Singapore, 2018. |
| 14 | ”High Speed FinFET Traff Comparator Based Function Generator.” | 2018 International conference on computation of power, energy, Information and Communication (ICCPEIC). IEEE, 2018. |
| 15 | ”High Speed low area 2D FIR filter using Vedic Multiplier ” | 2022 International conference on Advances in computer Engineering and Communication system.(Presented). |
| 16 | ”Breast cancer detection using deep learning model.” | 2022 International conference on Advances in computer Engineering and Communication system.(Presented). |
Book Chapters
- Grande NagaJyothi, and Sridevi Sriadibhatla. ”Asic implementation of low power, area efficient adaptive fir filter using pipelined da.” Microelectronics, Electromagnetics and Telecommunications. Springer, Singapore, 2019. 385-394. Citations-11
- Grande NagaJyothi,G.Anusha, Debanjan Kunda,” ASIC Implementation of Fixed-point iterative, Parallel and Pipeline CORDIC Algorithm”, SOCPRO. Springer,2019. Citations-2
- Grande Naga Jyothi, Gorantla Anusha,Debunjan Kunda,N.Dilip Kumar.,”Design of FINFET based DRAM cell for Low Power Applications”, CADEC ,2019. Citations-1
- Grande Nagajyothi,Sanapala Kishore R.Sakthevel ,”Comparative Review of MAC Architectures”, Soft Computing for Intelligent Systems 2021.