Dr. Nehru Kandasamy
Qualification : Ph.D. (Anna University, Chennai)
Designation : Professor
Details of Educational Qualification:
| Course | Specialization | Group | College Name/University | Year of Passing |
|---|---|---|---|---|
| Ph.D. | Information and Communication Engineering | Information and Communication Engineering | Anna University, Chennai, India. | 2014 |
| M.E. | VLSI Design | VLSI Design | R.M.K Engineering College, Chennai,Tamilnadu. | 2007 |
| B.E. | Electronics and Instrumentation Engineering | Electronics and Instrumentation Engineering | Erode Sengunthar Engineering College, Erode, Tamilnadu | 2005 |
List of Publications
| S.No | Title of the Paper | Full Details of Journal Name / Conference Name, Volume number, page number, Date |
|---|---|---|
| 1 | A Shannon based low power adder cell for Neural Network Training | IJET., Vol 2.No 3, pp.258-262, June 2010. |
| 2 | CLRCL Full adder based low power multiplier architectures | Vol. 3, ISSUE 1, IJVES. 2012. |
| 3 | Design of 64 bit parallel prefix adder using transmission gate | European Journal of Scientific Research, Volume 90,Issue 4,2012 (Scopus Indexed Journal) , Impact factor 0.125. |
| 4 | Low power High performance full adder | International journal of computer application in technology, Vol.49, No.2, pp.134 - 140, 2014 (Scopus Indexed Journal) , Impact Factor 0.773 |
| 5 | Analysis of 16 Bit Counter using GDI technique and CMOS logic, International Journal of Applied Engineering Research | Vol. 10 Issue 6, p16121-16128, 2015 (Scopus Indexed Journal) , Impact Factor 0.181. |
| 6 | Performance Analysis of Array Multiplier Using SPL and Control Input.Technique Based Adder Cells for Neural Networks | International Journal of Control Theory and Applications, Vol.8, No.5, pp. 2189-2194,2015 (Scopus Indexed Journal) . |
| 7 | Design of 16 Bit Vedic Multiplier Using Semi Custom and Full custom Approach | Journal of Engineering Science and Technology Review, Vol. 10, N0.2, pp.220-232, 2017. (Scopus Indexed Journal), Impact Factor 0.466. |
| 8 | Performance Analysis of Power Gating Techniques in 4-Bit SISO shift register circuits | Journal of Engineering Science and Technology , Vol.12 , No.12, 2017. (Scopus Indexed Journal). |
| 9 | Design of Low-Power Adders Using Double Gate & MTCMOS Technology | Journal of Theoretical and Applied Information Technology, VOL.95, NO.1,78-86,2017 (Scopus Indexed Journal). Impact Factor 0.387. |
| 10 | Investigation And Analysis Of Low Power Modified 14t Adder And 20t Adder Circuits | Far East Journal Of Electronics and Communications, VOL.17, NO.2,389-398, 2017 (Scopus Indexed Journal) , Impact Factor 0.490. |
| 11 | Design and Development of Coded OFDM based Digital Audio Broadcasting System using Concatenated Convolutional Turbo Codes | International Journl of Engineering and Technology, Vol. 9, No. 1, pp. 77-84, March 2017.(ISSN: 2319-8613, DOI: 10.21817/ijet/2017/v9i1/ 170901409) |
| 12 | Design of substrate integrated microwave horn antenna with constant aperture distribution | International Journal of Electronics Engineering, Vol. 8, Issue 2, pp. 5-12, 2016. (ISSN: 0973-7383 (Online), Google Scholar Indexed, Copernicus. Impact Factor: 2.5). |
| 13 | Comparative Analysis of CNTFET and CMOS Logic based Arithmetic Logic Unit | Journal of Nano and Electronic Physics, Impact factor 0.513 (Scopus Indexed). |
| 14 | Smart Sensor Network Based High Quality Air Pollution Monitoring System Using Labview | International Journal of Online Engineering. Vol. 13, No. 8, 2017 (Scopus Indexed Journal), Impact factor 0.31 |
| 15 | Cruise control of phase irrigation motor using SparkFun Sensor | International Journal of Online Engineering. Vol. 13, No. 8, 2017 (Scopus Indexed Journal), Impact factor 0.31 |
| 16 | Shadow detection and removal in aerial images using Gaussian mixture-based background and foreground segmentation algorithm. | International Journal of Civil Engineering and Technology, 2017 (Scopus Indexed Journal). |
| 17 | Saturation and non-saturation throughput and packet delay analysis of IEEE 802.11 DCF for AdHoc networks. | International Journal of Mechanical Engineering and Technology, 2017 (Scopus Indexed Journal) . |
| 18 | Design and Study the Characteristics of E-shaped Micro Strip Patch Antenna with Different Dielectric Substrates | International Journal of Applied Engineering Research ISSN 0973-4562 Volume 12, Number 19 (2017) pp. 8838- 8843, (Scopus Indexed Journal) , Impact Factor 0.181 |
| 19 | Analysis Of Dynamic Power Consumption In 4 Tap Fir Filter Using Sl Based Adder And Multiplier Circuits | ARPN Journal of Engineering and Applied Sciences , VOL. 12, NO. 20, pp.5847-50, 2017, (Scopus Indexed Journal) ,Impact Factor 0.391 |
| 20 | Simulation of Analog Modulation and Demodulation Techniques in Virtual Instrumentation and Remote Lab | International Journal of Online Engineering. Vol. 13, No. 10, 2017 (Scopus Indexed Journal), Impact factor 0.31. |
| 21 | Smart Sensor Network based Industrial Parameters Monitoring in IOT Environment using Virtual Instrumentation Server | International Journal of Online Engineering. Vol. 13, No. 11,pp.111-119,2017 (Scopus Indexed Journal), Impact factor 0.31. |
| 22 | Power Analysis Data Set for 4-Bit MOCLA Adder. | Data in Brief 16 (2018) 122–126.2017(Scopus Indexed Journal),Impact factor 0.201.https://doi.org/10.1016/j.dib.2017.11.017 |
| 23 | Design of a Low-Power ALU and Synchronous Counter Using Clock Gating Technique. | Progress in Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 564. Springer, Singapore. (scopus Indexed) |
| 24 | Low Power Delay Product 8-bit ALU Design using Decoder and Data Selector. | Majlesi Journal of Electrical Engineering, 12(1).(Scopus Indexed) |
| 25 | Performance Analysis of 4-Bit MAC Unit using Hybrid GDI &Transmission Gate based Adder and Multiplier Circuits in 180 nm & 90 nm Technology | Microprocessors and Microsystems. (SCI and SCI expanded Indexed) |
| 26 | Analysis of DCVS and MODL Logic in CLA. | Journal of Engineering and Applied Sciences, 13: 1844-1850.(SCOPUS Indexed) |
| 27 | USRP 2901 Based MIMO-OFDM Transciever | in Virtual and Remote Laboratory |
| 28 | Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis. | International Journal of Theoretical Physics, 1-14. (SCI and SCI expanded Indexed). |
| 29 | USRP 2901 Based FM transmitter with large file capabilities and Mobile Receiver in Virtual and Remote Laboratory | International Journal of Online Engineering (Accepted) (Scopus). |
| 30 | Intelligent Vehicular System with Speed Limit. | International Journal of Engineering & Technology, [S.l.], v. 7, n. 3.27, p. 20-23, aug. 2018. (Scopus). |
| 31 | Smart sensor network based fire rescue system design using lab VIEW. | International Journal of Recent Technology and Engineering 8(2), pp. 3372-3380, 2019. (Scopus) |
| 32 | Smart sensor network based atm management system using lab view. | International Journal of Engineering and Advanced Technology 8(5), pp. 2434-2444, 2019. (Scopus) |
| 33 | Ber analysis of concatenated levels of encoding in GFDM system using labview. | Indonesian Journal of Electrical Engineering and Computer Science 14(1), pp. 80-91, 2019. (Scopus) |
| 34 | USRP 2901-based SISO-GFDM transceiver design experiment in virtual and remote laboratory. | International Journal of Electrical Engineering Education. (SCI Indexed). (Article in Press). |
| 35 | Digital audio broadcasting based gfdm transceiver using software defined radio. | International Journal of Innovative Technology and Exploring Engineering 8(5), pp. 273-281, 2019. (Scopus) |
| 36 | Analysis of Self Checking and Self Resetting Logic in CLA and CSA Circuits Using Gate Diffusion Input Technique. | In 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) (pp. 1-6). IEEE. |
| 37 | A New Approach for Cyclic Combinational Circuit Using TGDI | 8th International Conference on Advances in Computing and Communication (ICACC-2018).(Accepted). (Scopus Indexed) |
| 38 | Design of low power ALU using 8T FA and PTL based MUX circuits | IEEE-International Conference on Advances in Engineering, Science and Management, ICAESM-2012, pp. 145– 149, 2012. (Scopus Indexed) |
| 39 | Design of 64 bit low power parallel prefix VLSI adder for high speed arithmetic circuits | published in IEEE International Conference on computing, communication and applications 2011ICCIC ,pp.1-4,2012. (Scopus Indexed) |
| 40 | Design of 4 bit up and down counter using gate diffusion input technique | published in IEEE – International Conference on computational intelligence and computing research , 2011. Pages :112-115. (Scopus Indexed) |
| 41 | Real Time SOC Based Low Cost Smart Sensor Using DWT On FPGA | accepted in IEEE Conference icecs 2016. |
| 42 | Performance Analysis of Low Power and High Speed 16-Bit CRC Generator Using GDI Technique | IEEE Conference ICACCS 2016. (Scopus Indexed). |
| 43 | Performance & Study of 16-Bit Vedic Multiplier using High Speed Adders | ICEMS 2016. |
| 44 | Design of scientific calculator using Labview | 4th International Conference on "Microelectronics, Circuits and Systems"Darjeeling, West Bengal, India,3rd and 4th June, 2017. |
| 45 | Performance Analysis of Array Multiplier Using SPL and Control Input Technique Based Adder Cells for Neural Networks | ICSCS ,19-20 Feb 2016. |
| 46 | Efficient parallel multiplier and accumulator architecture for high speed arithmetic | published in advances in engineering and technology,May 27th & 28th, 2011. |
| 47 | CLRCL full adder based low power multiplier architectures | published in ICICES 2012. |
| 48 | 64 bit parallel prefix adder for high speed arithmetic circuits | published in communication and computing, 2012. |
| 49 | low area hardware design of whirlpool hashing core using VHDL | published in Intelligent systems and control,4-5 Feb 2010 at karpagam college of engineering,Coimbatore. |
| 50 | Design of 64 bit low power parallel prefix adder in different word length- comparative study | published in NCSSS 2012. |
| 51 | Design and Implementation of low power arithmetic and logic unit | published in NCSSS 2012. |
| 52 | Power consumption analysis of various FIR filter architecture using TH March 2009. TANNER | published in innovations in communication and computing |
| 53 | Implementation of cluster formation algorithm using NS2 and VHDL | published in PCID on Feb 16-17,2007. |
FDP/Workshop Attended
- Attended one week FDP Program on ”Empowering Tomorrow's Mobility: AI-Driven Innovations for Electric Vehicles” CMR Institute of Technology from 04/12/2023 to 09/12/2023.
- Attended Faculty Development Program on ”Analog and Mixed Signal Design using Synopsys Tool” Synopsys, India from 26/06/2023 to 30/06/2023.
- Attended one week Faculty Development Program on System Design Through Verilog NPTEL, India from July to Sep 2023.
- Attended Workshop on Engineering Research Applications of Artificial Intelligence, Machine Learning and Internet of Things Using MATLAB, MITS , Madanapalle from 20-11-2023 to 24-11-2023.
- Attended One Week FDP Program on “Revolutionizing Tomorrow: Exploring Cutting Edge Trends in Integrated Circuits" IIIT SRI CITY from 30-04-2024 to 04-05-2024.
- Attended three days workshop on “Advances in Electron Device Technology for IoT and Communication” MITS, Madanapalle from 22-04-2024 to 24-04-2024.
- Attended Faculty Development Program on CMOS Digital VLSI Design, NPTEL, INDIA from January to March 2024.
- Attended webinar on Next Generation Technologies for Semiconductor Failure Analysis IEEE Certificate Program on 20/09/2023
- Attended Professional Development Program on A Full-Stack Viewof Probabilistic Computing With p-Bits: Devices, Architectures, and Algorithms on 05/02/2024.
- Attended Circuits and Systems Society Webinar on “Challenges and Directions in State of the Art Nanoelectronics , 27/09/2023.
FDP/STC Organized
- Organized one week short term training course on Free Softwares for ECE lab practices NITTTR, Chandigarh from 11-03-2024 to 15-03-2024
Seminar's Organized
- Organisedd three days National Seminar on “Recent Trends and Challenges in VLSI Circuits, Devices and Architectures” from 23-01-2024 to 25-01-2024.
- Organized one day IEEE VSB Program on “Basics of Research, Paper Writing, Patent Filing, Project Proposal Submission, 07-11-2023.
- Organised one day IEEE VSB Program on VLSI Design: Processes, Devices and Circuits, 9-9-2023
- Organised one day seminar on ”Role of AI in Medical Image Processing” Madanapalle Institute of Technology and Science, 26-06-2023
- Organized one day seminar on “Multi Gate Devices for VLSI Design” Madanapalle Institute of Technology and Science ,20-12-2022
- Organised one day seminar on “Solar Power Electric Vehicle” Madanapalle Institute of Technology and Science, 16-12-2022
- Organised one day seminar on ”Telehealth Technology – A new horizon in Health care”, Madanapalle Institute of Technology and Science, 13-12-2022
Student Program organized at Institute Level with MITS Affiliation
- Organized “ISRO START PROGRAMME 2023” from 20-07-2023 TO 07-08-2023, Madanapalle Institute of Technology and Science – NODAL CENTRE.