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Dr. Sarfraz Hussain

Qualification : Ph.D.

Details of Educational Qualification:

Course Specialization Group College Name/University Year of Passing
Ph.D. Electronics and Communication Engineering Electronics and Communication Engineering NERIST, Arunachal Pradesh 2021
M.Tech. Very Large Scale Integration Electronics and Communication Engineering NERIST, Arunachal Pradesh 2014
B.Tech. Electronics and Communication Engineering Electronics and Communication Engineering NEHU, Meghalaya 2010

Note : Students are advised to meet me in Room No : EB-215 D (Staff room) at any time other than my class hours mentioned in the below timetable for any discussions related to the subjects & research.

My Schedule for 2022-23

                                     

List of Publications

S.No Title of the Paper Full Details of Journal Name / Conference Name, Volume number, page number, Date
1 “Resolution-Selective and Resolution-Adaptive 2 to 8-bit Flash ADC for High-Speed Application Independent IC (HS-AIIC)” Journal of Circuits, Systems, and Computers, Under Revision, 2021. (SCI Indexed, Impact factor 1.33)
2 “Methodology and Comparative design of an efficient 4-bit Encoder with bubble error corrector for 1-GSPS Flash type ADC” IET Circuits, Devices & Systems, Vol. 14, Iss. 5, pp. 629-639, August 2020. DOI: 10.1049/iet-cds.2019.0499 (SCI Indexed, Impact factor 1.29)
3 “Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology” Proceedings of the 6th International Conference on Computers, Management & Mathematical Sciences (ICCM 2020), NERIST, Nirjuli, Arunachal Pradesh, India. 22-23 Dec. 2020, Vol. 1020, Issue 012022, pp- 1-7. IOP Conference Series: Materials Science and Engineering. DOI: 10.1088/1757-899x/1020/1/012022. IOP Publishing Ltd. (Scopus indexed) Online ISSN: 1757- 899X Print ISSN: 1757-8981
4 “A Study on Securing Data in Smart Healthcare Applications” 7th IEEE International Symposium on Smart Electronic Systems (IEEE 􀀀 iSES, formerly IEEE iNIS), Jaipur, Rajasthan, India, Dec. 2021, Accepted.
5 “Design of a Low Power and High Speed Wallace Tree Encoder for Flash ADC” Proceedings of the 5th International Conference on Computers & Management Skills (ICCM 2019), Nirjuli, Arunachal Pradesh, India, Jan. 2020. DOI: 10.2139/ssrn.3516639
6 “Comparison and Design of Dynamic Comparator in 180nm SCL Technology for Low Power and High Speed Flash ADC” 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 139-144, Bhopal, MP, India, Dec. 2017. DOI: 10.1109/iNIS.2017.37 (Scopus Indexed) (Under top 50 most read conference paper of iNIS)
7 “ANovel Low Power High Speed BEC for 2GHz Sampling Rate Flash ADC in 45nm Technology” 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), pp. 133-138, Bhopal, MP, India, Dec. 2017. DOI: 10.1109/iNIS.2017.36 (Scopus Indexed)
8 “Design of an efficient 8-bit flash ADC for optical communication receivers” 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), pp. 449-453, Chennai, TN, India, March 2016. DOI: 10.1109/ICEEOT.2016.7755560 (Scopus Indexed)
  • S. Hussain, R. Kumar and G. Trivedi, “Resolution Selective 2 to 6 - bit Flash ADC in 45nm Technology”, Electronic Systems and Intelligent Computing (ESIC). Lecture Notes in Electrical Engineering (LNEE), Vol. 686, pp. 475-483. Sept. 2020. Springer, Singapore. DOI: 10.1007/978-981-15-7031-5_45 (Scopus Indexed)